Cache memory is usually organized at multiple levels, such as L1 for level 1 and L2 for level 2, with L1 having the smallest storage capacity but the fastest memory speed. The data in L1, L2, and main memory can be accessed using 1, 10, and 100 clock cycles, respectively. When the cache miss rates in L1 and L2 are 5% and 50% respectively, what is the average memory access time in clock cycles?